Rambus Inc. announced it now offers a comprehensive and optimized interface solution designed for PCI Express (PCIe) 5.0, with backward compatibility to PCIe 4.0, 3.0 and 2.0. The Rambus PCIe 5.0 interface solution includes both PHY and digital controller for easy SoC integration and faster time to market.
With the PHY designed for an advanced 7nm process node, the integrated solution offers best-in-class power, performance and area thanks to the industry-proven engineering and signal integrity expertise of Rambus.
In addition to the PHY capability, the Rambus PCIe 5.0 solution includes a high-performance, digital controller core from recently acquired Northwest Logic. The Rambus PHY and controller are offered as a fully validated and integrated solution, or they can be licensed separately and used with third-party solutions. The entire solution is backed by Rambus design, integration and support services for first-time customer success.
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol.
With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate.
Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth.
Rambus PCIe 5.0 offering delivers integrated and co-validated PHY and digital controller for complete interface solution; comes built with Rambus’ industry-proven design methodology for PCIe interfaces; 32 GT/s bandwidth per lane with 128 GB/s bandwidth in x16 configuration; backward compatible to PCIe 4.0, 3.0 and 2.0; supports Compute Express Link interconnect; advanced multi-tap transceiver and receiver equalization compensate for more than 36dB of insertion loss; ideal power, performance and area capabilities; and supports performance-intensive applications including AI, data center, HPC, storage and 400GbE networking.
“Our high-speed SerDes and memory interface solutions make possible amazing advancements in performance-intensive applications in AI, data center, HPC, storage and networking,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “Now we’ve added PCIe 5 to our industry-leading portfolio of high-speed interface solutions giving chip makers another tool to unleash the power of their designs.”
The Rambus PCIe 5.0 solution is available globally in an advanced 7nm FinFET process.