Synopsys Inc. reduced on Wednesday the power and area of its DesignWare USB 2.0 Type-C Controller and PHY IP for cost-sensitive and energy-efficient Internet of Things (IoT) edge applications targeting 40-nanometer (nm) and 55-nm ultra-low power processes.
The IP cuts silicon area by up to 50 percent compared to competitive offerings, saving on average $0.03 per die. To extend battery life, the USB IP uses 30 percent lower active power compared to competing solutions and near 0 W of standby power.
The DesignWare USB 2.0 Type-C IP supports the IEEE 1801 standard Unified Power Format (UPF) to speed implementation and testing of power domains. In addition, Synopsys has simplified configuration options in the IP to reduce integration and verification effort by weeks or months.
The DesignWare USB 2.0 Type-C Host, Device and Dual-Role Device Controllers and PHYs are based on Synopsys USB 2.0 IP that has been certified more than 90 times and integrated in thousands of SoC designs shipping in billions of chips. The new DesignWare USB solution supports the USB Battery Charging v1.2 specification, delivering up to 1.5 A of current to IoT devices connected to a wall charger.
In addition, the DesignWare USB 2.0 Type-C IP supports advanced power management features, such as power supply gating and support for near 0 W standby current, to help designers reduce leakage for IoT devices. For the fastest, most efficient IC development, the IP eliminates the 80 percent of standard USB 2.0 configuration options that are not essential to IoT systems.
Apart from the DesignWare USB 2.0 Type-C Controllers and PHYs, Synopsys offers IP prototyping kits, IP software development kits and verification IP to enable early software development, reduce IP integration risk and speed time-to-market.
“Reducing energy consumption and system costs are critical for IoT applications,” said John Koeter, Synopsys’ vice president of marketing for IP and prototyping. “Synopsys is delivering a broad range of DesignWare IP optimized specifically for IoT applications, including the new USB 2.0 Type-C IP, to help designers extend battery life, reduce costs and enable additional functionality in their products.”
“To meet our customers’ stringent power and area requirements, our SoCs, which incorporate USB 2.0 functionality, must be significantly smaller and consume less power than competing options,” said SJ Choi, senior vice president, head of digital TV SoC R&D at SIC center, LG Electronics. “As the leader in USB IP, Synopsys understands our design challenges and consistently delivers USB solutions that meet our exact needs. Their IP, combined with their long track record of USB compliance and proven interoperability, allows us to mitigate our design risk and achieve first silicon success.”
“The continued proliferation of IoT edge devices requires more data to be delivered through USB interfaces with minimal power consumption in an extremely small form factor,” said Jeff Ravencraft, USB-IF president and COO. “Synopsys’ USB 2.0 IP solution has been specifically designed and optimized to address these requirements, which is critical for designers to quickly and easily integrate USB functionality into their IoT SoCs.”
The DesignWare USB 2.0 Type-C Device Controller IP includes packet FIFO controller which executes all USB commands in hardware that tracks endpoint information in the endpoint info block; processes data to and from UTMI+ PHY in the parallel interface engines; saves power by suspending and resuming controller operation in compliance with the USB specification; offers FIFO control logic for buffering data in and out of the controller while minimizing configuration, design, and verification time; apart from including control and status registers for reconfiguring the controller through firmware for maximum flexibility.
The bus interface unit comes with ARM AMBA High-performance bus (AHB) master for descriptor DMA controller with scatter/gather capability; reduces CPU interrupts; and enhances AHB throughput. The Hibernation Add-On option adds Wakeup and Power Control support for reduced power consumption by stopping the PHY reference clock when USB is suspended or the session is not valid. Further power reduction with AHB clock-gating and partial power- down methods.